1. Field of the Invention:
The present invention relates to a semiconductor device, and more particularly to a multi-chip package type semiconductor device having a plurality of semiconductor chips within a package.
2. Description of the Related Art:
A multi-chip package (MCP) type semiconductor device has a plurality of semiconductor chips within a package.
For example, an MCP type semiconductor device is disclosed in JP-A 2008-159718.
The MCP type semiconductor device disclosed in FIG. 8 of JP-A 2008-159718 has a wiring substrate (silicon substrate 30) and three semiconductor chips (electronic components 31) arranged in parallel on the wiring substrate. Those semiconductor chips have the same specification. For example, the semiconductor chips have the same height.
Meanwhile, an MCP type semiconductor device in which a chip-layered structure having a plurality of semiconductor chips stacked in the thickness direction of the semiconductor device is mounted within a package has been proposed and put into practical use according to recent trends of high density packaging of semiconductor devices and enhancement of functionality.
Referring to FIG. 1, an MCP type semiconductor device 700 having a chip-layered structure, as the related art of the present invention, includes a wiring substrate 10 and three semiconductor chips 711, 721, and 722 mounted on the wiring substrate 10. Among those semiconductor chips, the semiconductor chips 721 and 722 are stacked as semiconductor chip components in the height direction (thickness direction) of the semiconductor chips 721 and 722. Thus, the semiconductor chips 721 and 722 form a chip-layered structure 720. In FIG. 1, the reference numeral 12 denotes a connection pad, the reference numeral 13 a land, the reference numeral 16 a solder ball, the reference numeral 72 an electrode pad, the reference numerals 73 and 74 adhesive members, and the reference numeral 41 a wire.
For example, another MCP type semiconductor device having a chip-layered structure other than the semiconductor device shown in FIG. 1 is disclosed in FIG. 3 of JP-A 2008-159718. This semiconductor device has a plurality of components mounted symmetrically with respect to the centers of two wiring substrates (a substrate 3A and a substrate 3B) in order to suppress warp of the semiconductor device. However, this semiconductor device uses two wiring substrates (the substrate 3A and the substrate 3B). Therefore, the manufacturing cost of the semiconductor device increases.
In the MCP type semiconductor devices having a chip-layered structure according to the related art of the present invention, which include the example illustrated in FIG. 1, the thickness from an upper surface of a first semiconductor chip to a surface of a sealing member is different from the thickness from an upper surface of a chip-layered structure (a second semiconductor chip) to the surface of the sealing member. Accordingly, the sealing member is unbalanced on the wiring substrate. Thus, uneven torsion or strain is caused to the semiconductor device by shrinkage of the sealing member on curing. Such torsion or strain makes it difficult to mount the semiconductor device onto a motherboard.